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dear customers, about the change in the name such as "oki electric industry co. ltd." and "oki" in documents to oki semiconductor co., ltd. the semiconductor business of oki electric industry co., ltd. was succeeded to oki semiconductor co., ltd. on oc tober 1, 2008. therefore, please accept that although the terms and marks of "oki electric indust ry co., ltd.", ?oki electric?, and "oki" remain in the documents, they all have been changed to "oki semiconductor co., ltd.". it is a change of the company name, the co mpany trademark, and the logo, etc. , and not a content change in documents. october 1, 2008 oki semiconductor co., ltd. 550-1 higashiasakawa-cho, hachio ji-shi, tokyo 193-8550, japan http://www.okisemi.com/en/
? semiconductor md56v62800a 1/28 description the md56v62800a is a 4-bank 2,097,152-word 8-bit synchronous dynamic ram, fabricated in oki's cmos silicon-gate process technology. the device operates at 3.3 v. the inputs and outputs are lvttl compatible. features ? silicon gate, quadruple polysilicon cmos, 1-transistor memory cell ? 4-bank 2,097,152-word 8-bit configuration ? 3.3 v power supply, 0.3 v tolerance ? input : lvttl compatible ? output : lvttl compatible ? refresh : 4096 cycles/64 ms ? programmable data transfer mode C cas latency (1, 2, 3) C burst length (1, 2, 4, 8, full page) C data scramble (sequential, interleave) ? burst read single bit write capability ? cbr auto-refresh, self-refresh capability ? package: 54-pin 400 mil plastic tsop (type ii) (tsopii54-p-400-0.80-k) (product : md56v62800a-xxta) xx indicates speed rank. product family ? semiconductor md56v62800a 4-bank 2,097,152-word 8-bit synchronous dynamic ram preliminary family access time (max.) md56v62800a-8 md56v62800a-10 max. frequency 125 mhz 100 mhz 10 ns 9 ns t ac2 6 ns 9 ns t ac3 this version: oct. 1998 e2g1054-18-x3
? semiconductor md56v62800a 2/28 pin configuration (top view) v cc 1 v ss dq1 2 v cc q 3 nc 4 dq2 5 v ss q 6 nc 7 dq3 8 v cc q 9 nc 10 dq4 11 v ss q 12 nc 13 v cc 14 nc 15 we 16 cas 17 ras 18 cs 19 a13/ba0 20 a12/ba1 21 a10 22 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 dq8 v ss q nc dq7 v cc q nc dq6 v ss q nc dq5 v cc q nc v ss nc dqm clk cke nc a11 a9 a8 a0 23 a1 24 a2 25 32 31 30 a7 a6 a5 54-pin plastic tsop ( ii ) (k type) a3 26 v cc 27 29 28 a4 v ss pin name function system clock clock enable address row address strobe column address strobe write enable data input/output mask data input/output power supply (3.3 v) ground (0 v) data output power supply (3.3 v) data output ground (0 v) clk cke a0 - a11 ras cas we dqm dqi v cc v ss v cc q v ss q chip select cs bank select address a12, a13 no connection nc pin name function note: the same power supply voltage must be provided to every v cc pin and v cc q pin. the same gnd voltage level must be provided to every v ss pin and v ss q pin.
? semiconductor md56v62800a 3/28 pin description clk fetches all inputs at the "h" edge. cke masks system clock to deactivate the subsequent clk operation. if cke is deactivated, system clock will be masked so that the subsequent clk operation is deactivated. cke should be asserted at least one cycle prior to a new command. row & column multiplexed. row address: ra0 C ra11 column address: ca0 C ca8 ras cas we functionality depends on the combination. for details, see the function truth table. dqm masks the read data of two clocks later when dqm is set "h" at the "h" edge of the clock signal. masks the write data of the same clock when dqm is set "h" at the "h" edge of the clock signal. address dqi data inputs/outputs are multiplexed on the same pin. cs disables or enables device operation by asserting or deactivating all inputs except clk, cke and dqm. bank access pins. these pins are dedicated to select one of 4 banks. a12, a13 (ba1, ba0)
? semiconductor md56v62800a 4/28 block diagram clock buffer clk cke command buffers cs ras cas we dqm address buffers a0 - a13 command decoding logic mode register bank d row decoders word drivers memory cells column decoders sense amplifiers bank a bank b bank c dq1 - dq8 input buffers input data register output buffers output data register latency & burst controller control logic row address latches & refresh counter column address latches & counter
? semiconductor md56v62800a 5/28 electrical characteristics absolute maximum ratings (voltages referenced to v ss ) parameter unit symbol voltage on any pin relative to v ss rating v in , v out C0.5 to v cc + 0.5 v v cc supply voltage v cc , v cc q C0.5 to 4.6 v storage temperature t stg C55 to 150 c power dissipation p d * 1w short circuit current i os 50 ma operating temperature t opr 0 to 70 c *: ta = 25 c (voltages referenced to v ss = 0 v) parameter unit symbol power supply voltage v cc , v cc q input high voltage v ih input low voltage v il min. 3.0 2.0 C 0.3 v v v typ. 3.3 max. 3.6 v cc + 0.3 0.8 recommended operating conditions capacitance (v cc = 3.3 v, v bias = 1.4 v, ta = 25c, f = 1 mhz) parameter unit symbol input capacitance (cke, cs , ras , cas , we , dqm, a0 - a13) input/output capacitance (dq1 - dq8) c in c out 2.5 4 pf pf input capacitance (clk) c clk 2.5 pf 4 5 6.5 min. max.
? semiconductor md56v62800a 6/28 dc characteristics parameter condition version unit note cke others -8 -10 symbol output high voltage output low voltage input leakage current 2.4 C 5 v v m a i oh = C2 ma i ol = 2 ma v oh v ol i li 0.4 5 2.4 C 5 0.4 5 output leakage current C 5 m a i lo 5C 5 5 min. max. min. max. average power supply current (operating) ma 1, 2 cke 3 v ih t cc = min t rc = min no burst i cc 1 125 115 power supply current (stand by) ma 3 cke 3 v ih t cc = min i cc 2 30 30 average power supply current (clock suspension) ma 2 cke v il t cc = min i cc 3s 6 6 power supply current (burst) ma 1, 2 cke 3 v ih t cc = min i cc 4 165 155 power supply current (auto-refresh) ma 2 cke 3 v ih t cc = min t rc = min i cc 5 185 185 average power supply current (self-refresh) ma cke 0.2 v t cc = min i cc 6 2 2 average power supply current (power down) ma cke v il t cc = min i cc 7 2 2 average power supply current (active stand by) ma 3 cke 3 v ih , cs 3 v ih t cc = min i cc 3 60 50 ma 1, 2 cke 3 v ih t cc = min t rc = min t rrd = min no burst i cc 1d 175 165 bank one bank active both banks precharge both banks active both banks active one bank active both banks precharge both banks precharge one bank active both banks active notes: 1. measured with outputs open. 2. the address and data can be changed once or left unchanged during one cycle. 3. the address and data can be changed once or left unchanged during two cycles.
? semiconductor md56v62800a 7/28 mode set address keys notes: 1. a7, a8, a10, a11, a12 and a13 should stay "l" during mode set cycle. 2. when a9 = 1, a burst length for write operation is always 1 regardless of the burst lengths set by a0, a1 and a2. power on sequence 1. with inputs in nop state, turn on the power supply and start the system clock. 2. after the v cc voltage has reached the specified level, pause for 200 m s or more with the input kept in nop state. 3. issue the precharge all bank command. 4. apply a cbr auto-refresh eight or more times. 5. enter the mode register setting command. a6 a5 a4 cl a3 bt a2 a1 a0 bt = 0 bt = 1 cas latency burst type burst length a9 0 1 burst write single bit write write burst length write burst length 000 reserved 0 sequential 000 1 1 001 1 interleave 001 2 2 010 010 4 4 011 011 8 8 1 2 3 100 reserved 100 reserved reserved 101 reserved 101 reserved reserved 110 reserved 110 reserved reserved 111 reserved 111 full page reserved
? semiconductor md56v62800a 8/28 ac characteristics clock "h" pulse time clock "l" pulse time input setup time input hold time output low impedance time from clock output high impedance time from clock output hold from clock ras cycle time ras precharge time ras active time write recovery time refresh time power-down exit set-up time ras to cas delay time t ch t cl t si t hi t rc t rp t ras t wr t ref t pde t rcd t olz t ohz 3 3 2 1 80 30 50 8 t si + 1 clk 20 3 100,000 64 8 3 3 3 1 90 30 60 10 t si + 1 clk 30 3 100,000 64 8 ns ns ns ns ns ns ns ns ms ns ns ns ns ras to ras bank active delay time t rrd 16 20 ns input level transition time t t 33ns t oh 3 3 ns 3 cas to cas delay time (min.) l ccd 1 1 cycle 11 clock disable time from cke l cke cycle 22 data output high impedance time from dqm l doz cycle 00 data input mask time from dqm l dod cycle 00 data input time from write command l dwd cycle data output high impedance time from precharge command 33 active command input time from mode register set command input (min.) l mrd cycle 22 l roh cycle access time from clock cl = 3 cl = 2 6 10 9 9 ns ns 3, 4 3, 4 parameter md56v62800a-8 md56v62800a-10 clock cycles time cl = 3 cl = 2 symbol t cc min. 8 12 max. min. 10 15 max. unit ns ns note note 1, 2 22 write command input time from output l owd cycle t ac 33 cycle 11 cycle cl = 1 22 27 ns cl = 1 24 30 ns 3, 4 cl = 3 cl = 2 cl = 1
? semiconductor md56v62800a 9/28 notes : 1. ac measurements assume that t t = 1 ns. 2. the reference level for timing of input signals is 1.4 v. 3. output load. output z = 50 w 50 pf 50 w 1.4 v 4. the access time is defined at 1.4 v. 5. if t t is longer than 1 ns, then the reference level for timing of input signals is v ih and v il .
? semiconductor md56v62800a 10/28 timing waveform read & write cycle (same bank) @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we ra ca0 qa0 t oh t rc cs t rp t rcd a12 a10 rb cb0 qa1 qa2 qa3 db0 db1 db2 db3 t ohz row active read command prechar g e command row active write command precharge command ra rb t wr t ac a13 dqm
? semiconductor md56v62800a 11/28 single bit read-write-read cycle (same page) @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we ra ca qa cs a12 a10 cb cc db qc row active read command read command write command precharge command t ch t cc t cl t si t hi t si t hi t si l ccd t hi t si t si t hi ra t hi t si t ac t olz t ohz t hi t si t oh high l owd a13 dqm
? semiconductor md56v62800a 12/28 a12 0 operation after the end of burst, bank a holds the idle status. a13 0 0 0 after the end of burst, bank b holds the idle status. 1 1 after the end of burst, bank a is precharged automatically. after the end of burst, bank b is precharged automatically. 0 0 a10 0 0 1 1 1 after the end of burst, bank c holds the idle status. 0 0 1 after the end of burst, bank d holds the idle status. 1 1 after the end of burst, bank c is precharged automatically. after the end of burst, bank d is precharged automatically. 1 1 0 0 1 1 * notes: 1. when cs is set "high" at a clock transition from "low" to "high", all inputs except cke and dqm are invalid. 2. when issuing an active, read or write command, the bank is selected by a12 and a13. 3. the auto precharge function is enabled or disabled by the a10 input when the read or write command is issued. a13 0 1 active, read or write bank a bank b a12 0 0 0 1 bank c bank d 1 1 4. when issuing a precharge command, the bank to be precharged is selected by the a10, a12 and a13 inputs. a12 0 0 1 a13 0 1 0 operation bank a is precharged. bank b is precharged. bank c is precharged. a10 0 0 0 1 x 1 x bank d is precharged. all banks are precharged. 0 1 5. the input data and the write command are latched by the same clock (write latency = 0). 6. the output is forced to high impedance by (1 clk + t ohz ) after dqm entry.
? semiconductor md56v62800a 13/28 page read & write cycle (same bank) @ cas latency = 2, burst length = 4 * notes: 1. to write data before a burst read ends, dqm should be asserted three cycles prior to the write command to avoid bus contention. 2. to assert row precharge before a burst write ends, wait t wr after the last write data input. input data during the precharge input cycle will be masked internally. clk 012345678910111213141516171819 cke ras cas addr dq we ca0 cb0 cs a12 a10 cc0 cd0 qa0 read command write command prechar g e command t wr bank a active qa1 qb0 qb1 dc0 dc1 dd0 read command write command high l ccd *note2 *note1 a13 l owd dqm
? semiconductor md56v62800a 14/28 read & write cycle with auto precharge @ burst length = 4 clk 012345678910111213141516171819 cke ras cas addr we dq raa cs a12 a10 rdb caa row active (a-bank) row active ( d-bank ) a-bank precharge start d bank write with auto precharge cdb cas latency = 2 dq cas latency = 3 qaa0 qaa1 qaa2 qaa3 ddb0 ddb1 ddb2 ddb3 qaa0 qaa1 qaa2 qaa3 ddb0 ddb1 ddb2 ddb3 a bank read with auto precharge d bank precharge start point high t rrd a-bank precharge start t wr raa rdb a13 dqm dqm
? semiconductor md56v62800a 15/28 bank interleave random row read cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we raa caa cs a12 a10 qaa0 row active (a-bank) row active ( a-bank ) read command (c-bank) precharge command (c-bank) t rc raa t rrd rcb ccb rac cac rcb rac qaa1 qaa2 qaa3 qcb0 qcb1 qcb2 qcb3 qac0 qac1 qac2 read command (a-bank) row active (c-bank) precharge command ( a-bank ) read command (a-bank) high qac3 a13 dqm
? semiconductor md56v62800a 16/28 bank interleave random row write cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we raa caa cs a12 a10 daa0 row active (a-bank) precharge command (a-bank) raa rbb cbb rac cac daa1 daa2 daa3 dbb0 dbb1 dbb2 dbb3 dac0 dac1 write command (a-bank) row active (b-bank) rac rbb write command (b-bank) precharge command (a-bank) row active (a-bank) precharge command ( b-bank ) write command (a-bank) high a13 dqm
? semiconductor md56v62800a 17/28 clk 012345678910111213141516171819 cke ras cas addr dq we raa caa cs a12 a10 qaa0 row active (a-bank) read command ( a-bank ) raa rcb ccb cac ccd qaa1 qaa2 qaa3 qcb0 qcb1 qcb2 qcb3 qae0 qae1 read command ( a-bank ) row active (c-bank) rca read command ( c-bank ) read command ( a-bank ) read command (c-bank) cae qac0 qac1 qcd0 qcd1 precharge command (a-bank) high l roh *note1 a13 dqm bank interleave page read cycle @ cas latency = 2, burst length = 4 *note: 1. cs is ignored when ras , cas and we are high at the same cycle.
? semiconductor md56v62800a 18/28 bank interleave page write cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we rba cba cs a12 a10 dba0 row active (b-bank) precharge command ( all banks ) rba rdb cdb cbc cdd dba1 dba2 dba3 ddb0 ddb1 ddb2 ddb3 dbc0 dbc1 write command ( b-bank ) row active (d-bank) rdb write command ( d-bank ) write command ( b-bank ) write command (d-bank) ddd0 high a13 dqm
? semiconductor md56v62800a 19/28 bank interleave random row read/write cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we raa caa cs a12 a10 qaa0 row active (a-bank) raa rcb ccb rac qaa1 qaa2 qaa3 read command ( a-bank ) row active (c-bank) precharge command ( a-bank ) cac rac rcb dcb0 dcb1 dcb2 dcb3 qac0 qac1 qac2 qac3 write command (c-bank) row active ( a-bank ) read command (a-bank) high a13 dqm
? semiconductor md56v62800a 20/28 bank interleave page read/write cycle @ cas latency = 2, burst length = 4 clk 012345678910111213141516171819 cke ras cas addr dq we caa0 qac3 cs cdb0 cac0 a12 a10 high read command ( a-bank ) write command ( d-bank ) read command ( a-bank ) ddb3 qaa3 qaa2 qaa1 qaa0 ddb2 ddb1 ddb0 qac2 qac1 qac0 a13 dqm
? semiconductor md56v62800a 21/28 clock suspension & dqm operation cycle @ cas latency = 2, burst length = 4 clock suspension clk 012345678910111213141516171819 cke ras cas addr dq we ra cs ca cb a10 row active qb1 qb0 read command read command read dqm write command clock suspension write dqm cc t ohz dc2 dc0 qa1 qa0 qa2 t ohz write dqm *note1 ? *note1 dqm *note3 ? *note2 a12 a13 read dqm ra *notes: 1. when clock suspension is asserted, the next clock cycle is ignored. 2. when dqm is asserted, the read data after two clock cycles is masked. 3. when dqm is asserted, the write data in the same clock cycle is masked.
? semiconductor md56v62800a 22/28 read interruption by precharge command @ burst length = 8 we clk 012345678910111213141516171819 cke ras cas addr dq cs ca a12 a10 high row active read command prechar g e command qa3 qa2 qa1 qa0 dq cas latency = 3 cas latency = 2 qa4 qa3 qa2 qa1 qa0 qa4 ra qa5 ra a13 dqm dqm qa5 i roh i roh
? semiconductor md56v62800a 23/28 power down mode @ cas latency = 2, burst length = 4 *notes: 1. when all banks are in precharge state, and if cke is set low, then the md56v62800a enters power-down mode and maintains the mode while cke is low. 2. to release the circuit from power-down mode, cke has to be set high for t pde (t si + 1 clk) or more. clock suspention exit clk 012345678910111213141516171819 cke ras cas addr dq we cs a12 a10 qa2 qa1 qa0 t si t pde t si t si ra ca row active power-down entry power-down exit clock suspention entr y read command precharge command *note1 *note2 ra a13 dqm
? semiconductor md56v62800a 24/28 self refresh cycle clk 012 cke ras cas addr dq we cs a12 a10 t si hi - z hi - z self refresh entr y self refresh exit row active ra ra bs a13 bs t rc dqm
? semiconductor md56v62800a 25/28 mode register set cycle clk 012345 012345678910 cke ras cas addr dq we cs key ra mrs high high hi - z hi - z new command auto refresh t rc 6 11 12 l mrd auto refresh dqm auto refresh cycle
? semiconductor md56v62800a 26/28 function truth table (table 1) (1/2) current state 1 cs ras cas we ba addr hxxxx x lhhhx x l h h l ba x l h l x ba ca l l h h ba ra l l h l ba a10 lllhx x hxxxx x lhhxx x l h l h ba ca, a10 l h l l ba ca, a10 l l h h ba ra l l h l ba a10 lllxx x hxxxx x lhhhx x l h h l ba x l h l h ba ca, a10 l h l l ba ca, a10 l l h h ba ra l l h l ba a10 lllxx x hxxxx x lhhhx x l h h l ba x l h l h ba ca, a10 l h l l ba ca, a10 l l h h ba ra l l h l ba a10 hxxxx x lhhhx x l h h l ba x l h l h ba ca, a10 lhllx x l l h x ba ra, a10 lllxx x idle row active read write read with auto precharge hxxxx x lhhhx x l h h l ba x l h l h ba ca, a10 lhllx x l l h x ba ra, a10 lllxx x write with auto precharge action nop nop illegal 2 illegal 2 row active nop 4 auto-refresh or self-refresh 5 nop nop read write illegal 2 precharge illegal nop (continue row active after burst ends) nop (continue row active after burst ends) term burst term burst, start new burst read term burst, start new burst write illegal 2 term burst, execute row precharge illegal nop (continue row active after burst ends) nop (continue row active after burst ends) term burst term burst, start new burst read term burst, start new burst write illegal 2 term burst, execute row precharge illegal nop (continue burst to end and enter row precharge) nop (continue burst to end and enter row precharge) illegal 2 illegal 2 illegal illegal 2 illegal nop (continue burst to end and enter row precharge) nop (continue burst to end and enter row precharge) illegal 2 illegal 2 illegal illegal 2 lllxx x illegal llll op code mode register write l
? semiconductor md56v62800a 27/28 function truth table (table 1) (2/2) notes: 1. all inputs are enabled when cke is set high for at least 1 cycle prior to the inputs. 2. illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. satisfy the timing of l ccd and t wr to prevent bus contention. 4. nop to bank precharging or in idle state. precharges activated bank by ba or a10. 5. illegal if any bank is not idle. current state 1 cs ras cas we ba addr hxxxx x lhhhx x l h h l ba x l h l x ba ca l l h h ba ra l l h l ba a10 lllxx x hxxxx x lhhhx x l h h l ba x l h l x ba ca l l h h ba ra l l h l ba a10 lllxx x hxxxx x lhhhx x l h h l ba x l h l x ba ca l l h h ba ra l l h l ba a10 lllxx x hxxxx x lhhxx x lhlxx x llhxx x lllxx x hxxxx x lhhhx x lhhlx x lhlxx x llxxx x precharge write recovery row active refresh mode register access action nop --> idle after t rp nop --> idle after t rp illegal 2 illegal 2 illegal 2 nop 4 illegal nop nop illegal 2 illegal 2 illegal 2 illegal 2 illegal nop --> row active after t rcd nop --> row active after t rcd illegal 2 illegal 2 illegal 2 illegal 2 illegal nop --> idle after t rc nop --> idle after t rc illegal illegal illegal nop nop illegal illegal illegal abbreviations ra = row address ba = bank address nop = no operation command ca = column address ap = auto precharge
? semiconductor md56v62800a 28/28 current state (n) cken-1 cs ras cas we addr h xxxx x l hxxx x l lhhh x llhhlx llhlxx lllxxx l xxxx x h xxxx x l hxxx x l lhhh x llhhlx llhlxx lllxxx l xxxx x h xxxx x h hxxx x h lhhh x hlhhlx hlhlxx hllhlx h lllh x h xxxx x h xxxx x l xxxx x l xxxx x self refresh power down all banks idle 6 any state other action invalid exit self refresh --> abi exit self refresh --> abi illegal illegal illegal nop (maintain self refresh) invalid exit power down --> abi exit power down --> abi illegal illegal illegal 6 nop (continue power down mode) refer to table 1 enter power down enter power down illegal illegal illegal enter self refresh refer to operations in table 1 begin clock suspend next cycle enable clock of next cycle continue clock suspension cken x h h h h h l x h h h h h l h l l l l l l h l h l (abi) than listed above h llll x illegal l l xxxx x nop l function truth table for cke (table 2) note: 6. power-down and self refresh can be entered only when all the banks are in an idle state.

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